Figure 3 | NPG Asia Materials

Figure 3

From: Using binary resistors to achieve multilevel resistive switching in multilayer NiO/Pt nanowire arrays

Figure 3

(a) Renormalized current I/Imax=G/Gmax versus the number of voltage pulses n. The experimental data for the initial run are shown in red squares and those for the second run after reset are shown in green diamonds. The blue curve is the theoretical prediction from the binary-resistor model. The resistor ratio R/r=Gmax/Gmin=72 444 is extracted from experimental data, and the estimated number of units in each wire is Nl≈100. The fitting parameter is the binary-flip probability p fitted to the value p=1.9% here. (b) A schematic diagram of the multilevel memory effect induced by voltage pulses as described by the binary-resistor model.

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