Figure 3: Graphene–ferroelectric reconfigurable logic-gate metadevice.
From: Graphene–ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations
(a) Schematic representation of the graphene–ferroelectric reconfigurable logic-gate metadevice composed of a top THz transparent electrode (top; TTE, T), a ferroelectric polymer layer (2.1 μm, represented by green), a single-layer graphene, hexagonal MAs, a ferroelectric polymer layer (2.1 μm, represented by green), a bottom THz transparent electrode (bottom; TTE, B) and a polyimide layer (1 μm, represented by light red) as the substrate. Polarization of the incident THz is perpendicular to the two TTE lines. (b) Schematic representation of the four kinds of polarization alignments for input logic states. Red arrow implies an application of positive pulsed gating voltage for logic state 1 and blue arrow refers to the application of negative pulsed gating voltage for logic state 0. (c) Schematic representation of the transmission spectra for input logic states. For each input logic state, the relationship fR(0,0)<fR(0,1)=fR(1,0)<fR(1,1) is satisfied in the graphene–ferroelectric reconfigurable logic-gate metadevice because of p-doped graphene. A frequency of fREAD was designated for data reading and two reference transmission amplitudes, TREF1 and TREF2 were defined to execute AND (complementary NOR) and OR (complementary NAND) gate operations. For AND gate operation, the reference transmission amplitude is set to TREF1. For OR gate operation, the reference is TREF2. (d) Experimental transmission amplitude (TA) measured at 0.5 THz for the four types of logic inputs in the AND/OR gates, the XOR gate and the two-bit DAC.
