Figure 4: Processes of writing and erasing a nanowire at the LAO/TiO₂-STO heterointerface on Si.

(a) Schematic diagram of the 'writing' process used to generate conducting nanostructures at the LAO/TiO₂-STO heterointerface. (b) Electrical conductance between two electrodes during c-AFM writing with V_tip=+4 V. As the c-AFM tip reaches the second electrode, the conductance increases abruptly. The c-AFM tip travels along the x-direction as noted in the figure, with a speed of 400 nm/s relative to the structure. (c) Schematic diagram of the 'erasing' process by cutting the nanowire generated in the writing process. (d) As the c-AFM tip biased at −4 V scans cross the nanowire, the conductance decreases drastically. The c-AFM tip travels at a speed of 10 nm s⁻¹ along the y-direction, as indicated. The width of the nanowire presented in the inset is quantified by fitting the erase curve with a function G(x)=G₀−G₁tanh(x/h), with the following best-fit parameters: G₀=0.40 nS, G₁=0.44 nS and h=6.0 nm. The deconvolved differential conductance (dG/dx)*⁻¹ is shown in red and has a half-width maximum of 6.9 nm (+4 V wire).