Figure 1: Device structure and memory characteristics of the TRAM.
From: Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio
(a) Schematic of the two-terminal TRAM with monolayer MoS2 as a semiconducting channel at the top, h-BN as a tunnelling insulator in the middle and monolayer graphene as a floating gate, charge tunnelling between drain and graphene is shown by red arrow. (b) Band diagrams of drain (D)/h-BN/graphene (Gr), the dashed line arrows indicate the tunnelling direction of electrons and holes. Electrons are tunnelled from the drain to graphene at the Vds≤−6 V (Programme) and holes are tunnelled from h-BN to graphene at Vds≥6 V (Erase) states. (c) Atomistic schematic for the TRAM heterostructure of the monolayer MoS2/multilayer h-BN/monolayer graphene (left side) and cross-sectional bright-field scanning transmission electron microscope image and energy-dispersive X-ray spectroscopy elemental mapping of the TRAM heterostructure with 10-nm h-BN (right side). Scale bar is 5 nm. (d) Typical I–V curve of the TRAM with 5.5-nm thick h-BN. The current sweep by sweeping Vds is shown as a dashed line. The current sweep can be separated into four stages: (i) Programme, (ii) Read, (iii) Erase and (iv) Read. Channel length and channel width of the device are 4 and 2 μm, respectively. (e) Repeated Erase/Read/Programme/Read sequence with a drain voltage of +6 V/+0.1 V/−6 V/+0.1 V, respectively. The pulse width was 0.01 s.
