Figure 3: Transition from 4e2/h conductance to hard superconducting gap.

(a) Differential conductance, G, in Device 1 as a function of gate voltage Vg and source-drain voltage bias Vsd. (b) Vertical cuts in a in the tunnelling (red line) and one-channel (blue line) regime. Supplementary Figure 1 shows data from a lithographically similar device on a wafer with no InGaAs barrier (that is, b=0 nm) between the top layer Al and the InAs 2DEG. (c) Differential conductance at zero source-drain voltage, G(Vsd=0 mV), versus averaged differential conductance at finite source-drain voltage, G(|Vsd|>0.8 mV). Red and blue circles indicate data corresponding to cuts in b. Green line is the theoretically predicted conductance in an Andreev enhanced QPC (equation (1) with no fitting parameters).