Figure 5: Experimental demonstration of intra- and inter-layer sneak path blocking in stacked crossbar arrays.

(a) Schematic of the twp-layer stacked memristor crossbar array where the two layers of devices are electrically isolated by SOG. The red line is the expected current path during the readout of the selected device (red), while the blue line shows one typical intra-layer sneak path being blocked by a reverse biased cell. (b) Optical image of the two-layer stacked 8 × 8 memristors array with the outer contact pads connecting with the 1st layer devices while the inner pads with the second layer devices. (c) The colour map of the readout current by read a voltage of +2 V for the two layers stacked memristors crossbar array. Yellow represents higher read current and lower-resistance state while red the opposite. Before reading, the array was programmed into ASCII code representing ‘umass’ and ‘amherst’ respectively. The remaining cells were programmed into LRS to emulate the worst-case scenario with maximum sneak path current. The bits were read out correctly which proves the effective blocking of the intra-layer sneak path current by the built-in diode. (d) Schematic of the two-layer stacking with shared electrodes with adjacent layers. The reverse biased diode along the inter-layer sneak path (blue) prevents the inter-layer sneak path current, while the red line shows the expected path during the readout of selected device (red). (e) Optical image of the two-layer stacked crossbar array with shared electrodes. The connection of the contact pads was labelled in the image. (f) The experimental measurement result in a 2 × 2 sub-array shows that, in the worst-case scenario, the only HRS cell in the first layer can be readout correctly although all other cells are in LRS. This result confirms the successful suppression of the inter-layer sneak path current in the array. Scale bars, 50 μm. SOG, spin-on glass.