Figure 2: Device geometry and electronic properties of MoS2 TFTs.
From: High-mobility and low-power thin-film transistors based on multilayer MoS2 crystals
(a) The device geometry of a back-gated MoS2 TFT. The TFT device was measured at T=300 K. The device geometries are: W/L=4/7 μm, tox=50 nm and tch=30 nm. (b) Drain current versus back gate bias showing ~106 on/off ratio and ~80 mV per decade subthreshold slope. (c) Drain current versus drain bias showing current saturation. (d) Same as (c), including a long-channel model (red lines) showing excellent agreement between the TFT model and measured device behaviour.
