Figure 1: Experimental setup and a conductance-voltage spectrum.
From: Probing the electronic structure at semiconductor surfaces using charge transport in nanomembranes
(a) Schematic diagram of the van der Pauw measurement on a Si NM. The device mesa area is 4 × 4 mm2. The Si substrate serves as a back gate. (b) Image showing a sample mounted on the Mo sample holder. (c) Conductance as a function of back-gate voltage VG for a 120-nm thick Si NM after hydrofluoric acid (HF) treatment. The data are plotted in linear (left) and log (right) scales. The flat-band voltage VFB and the threshold voltage VTH are extracted from linear extrapolations of the curve. Surface electrical information is determined from the low-conductance region (between VFB and VTH, shaded in blue).
