Figure 1: Device architecture and addition energy spectrum.
From: Spin-valley lifetimes in a silicon quantum dot with tunable valley splitting
(a) Schematic (top view) of the device’s gate layout. Different colours represent different layers within the gate stack. (b) Schematic diagram of the single-lead QD (left) and SET detector (right). Regions where an electron layer is formed are coloured in orange. The read-out signal (ISET) is sensitive to the QD charge state due to the QD/SET capacitive coupling (Ccpl). (c) Device cross-sectional schematic. An electron layer is formed underneath the positively biased gates: R1 and R2 define the QD reservoir; P controls the QD population, and ST the sensor’s island. The SiO2 layer (in purple) thickness and plunger gate width are indicated. (d) Energy diagram showing qualitatively the conduction band profile in the device. Electrons accumulate wherever the gate bias lowers the conduction band below the Fermi level, EF. (e) Charging energy as a function of electron number. Spikes corresponding to complete 2D shell filling are observed. (f) Schematic of electron filling for two-valley 2D Fock–Darwin states. Each state can hold two electrons of antiparallel spin and is identified by a pair of quantum numbers (n,l) and its valley occupancy (v).
