Figure 3: Suspended graphene devices.

(a) 3-dimensional illustration of the device fabrication consisting of the following steps: (1) bottom gates are realized by standard e-beam lithography on a doped Si wafer with 300-nm-thick SiO₂ top layer and (2) covered by a 700-nm-thick LOR (lift-off resist) layer. (3) Graphene is exfoliated on a separated wafer covered by a stack of polyvinyl alcohol/PMMA, and then aligned to the bottom gates and transferred. (4) Contacts to the graphene are then realized with standard e-beam lithography followed by an evaporation of 50 nm palladium. (5) Finally, the device is suspended by selectively exposing the LOR with a large dose and developing it. (b) Optical image of several junctions defined within the same graphene flake indicated by white dashed lines. Bottom gates are in yellow and ohmic contacts in blue. The LOR resist appears in dark green. Scale bar, 5 μm. (c) Scanning electron microscopic image of three graphene p–n junctions in a row. Bottom gates are shown in yellow and contacts in light blue. Scale bar, 1.2 μm.