Figure 1: TaO y /Ta 2 O 5–x resistive switching and As-Te-Ge-Si-N TS devices.
From: A plasma-treated chalcogenide switch device for stackable scalable 3D nanoscale memory
(a) Idealized schematic of 3D-stacked memory structure using switch and memory element in crossbar array structure with enlarged view of memory cell. (b) I-V TS operation of the switch device (As-Te-Ge-Si-N) in the crossbar array. (c) I-V non-volatile switching operation of the memory device (TaOy/Ta2O5–x) in the crossbar array. (d) A cross-sectional TEM image of the 1S–1R with W/AlOx/TaOy/Ta2O5–x/Pt/TiN/As-Te-Ge-Si-N/TiN-stacked structure. Scale bar, 100 nm. (e) I-V characteristics of combined switch and memory device structure described with reduced leakage current at below ±1 V (readout margin for data reading in crossbar array).
