Figure 4: Device scalability demonstrated in scanning electron microscopy and scanning transmission electron microscopy images.
From: A plasma-treated chalcogenide switch device for stackable scalable 3D nanoscale memory
(a) Scanning electron microscopy (SEM) image of (500 nm)2 cell size with the inset showing an 8 × 8 array of 500 nm switch devices. Scale bar, 500 nm. (b) SEM image of a single (30 nm)2 cell-size device. The inset shows a shrunk image with top and bottom electrodes. Scale bar, 100 nm. (c) Cross-sectional scanning transmission electron microscopy of (30 nm)2 cell size. Scale bar, 30 nm. (d) Switching behaviour of (100 um)2, (50 um)2 and (10 um)2 cell-size devices with TiN electrodes. (e) Switching behaviour of (250 nm)2, (100 nm)2, (50 nm)2 and (30 nm)2 cell-size devices with Ti electrodes.
