Figure 2: Circuit diagram and device DC performance.

(a) Circuit schematic of three-stage graphene receiver IC comprising 11 active and passive components. (b) Optical micrograph of an IC under testing. The circuit has the dimension of 1,020 × 600 μm². Scale bar, 100 μm. (c) Photo of a fully processed graphene IC chip. (d) Drain currents as a function of gate biases for three transistors in one circuit and (e) their width normalized transconductances. The drain biases were −1 V. (f) Drain currents as a function of drain biases and (g) width normalized output conductances from the same devices. The gate biases were 0.25 V for both devices T1 and T2, and 0.75 V for device T3.