Figure 3: Vertical OFETs based on graphene-C8-BTBT heterostructures.
(a) Room temperature Jds−Vg characteristics of a device with ~15 nm thick (5-layer) C8-BTBT. From top to bottom, Vds=2 V and 1 V, respectively. (b) Room temperature Jds−Vds characteristics of the same device in a. From top to bottom, Vg=−100 V, −90 V, −80 V, −70 V and 0 V, respectively. Inset shows the device schematics. The source (S), drain (D) and gate (G) terminals are marked. (c) Energy band diagrams of the vertical OFET under various bias conditions. The band diagram under Vds=0 and Vg=0 is plotted in Supplementary Fig. 29. (d) Arrhenius plot (symbols) of normalized Jds of the same device in a under Vg=−100 V. From top to bottom, Vds=2 V, 1.6 V, 1.2 V and 0.8 V, respectively. The plot clearly shows two regimes: thermionic emission at high temperatures and tunnelling at low temperatures. Lines are theoretical fittings of the thermionic emission current. The extracted ΦSB are plotted in the inset as a function of Vds1/2 (symbols), with a linear fitting (line). (e,f) Output voltage levels of an AND (e) and OR (f) gate comprised two vertical diodes. The insets show the circuit diagrams. The pull-up resistor for the AND gate and the pull-down resistor for the OR gate are both 5 × 109 Ohms. During the operation of both logic gates, Vg=−100 V, Vdd=4 V.
