Figure 1: Quantum processor and gate sequence for implementing and characterizing bit-flip QEC by stabilizer measurements.
From: Detecting bit-flip errors in a logical qubit using stabilizer measurements
(a) Photograph of the processor (scale bar on the bottom-right indicates 1 mm) showing the position and interconnections of data qubits (Dt, Dm and Db), ancilla qubits (At and Ab), buses (Bt and Bb) and dedicated readout resonators. These resonators couple to one common feedline to which all readout and microwave control pulses are applied18. Flux-bias lines (ports 2–5 and 7) allow control of the qubit transition frequencies on nanosecond timescale (Supplementary Fig. 1). Details of the processor, including fabrication, parameters and performance benchmarks are provided in Methods and Supplementary Table 1. (b) Block diagram for characterizing bit-flip QEC by parallelized parity measurements of pairs (Dt, Dm) and (Dm, Db). The Dm state 
is first encoded into the logical qubit state 
. Coherent or incoherent bit-flip errors are then introduced on data qubits with independent single-bit-flip probability perr. Parallelized ZtZm and ZmZb stabilizer measurements discretize these errors and the two-bit measurement result PtPb is interpreted as signalling either no error or error on one qubit. (c) Gate sequence implementing the stabilizer measurements by parallelized interaction with ancilla qubits and projective ancilla measurements. Each ancilla is prepared in a superposition state that is transferred to the respective bus with an iSWAP gate (diagonal lines). Consecutive CPHASE gates between each bus and the coupled data qubits (vertical lines) encode the data-qubit parity in the quantum phase of the bus superposition state. The final iSWAP transfers this state to the ancilla, and the latter is then projectively measured in the |±〉 basis. Halfway through the interaction step, a refocusing π pulse is applied to Dm to reduce inhomogeneous dephasing.
