Figure 2: p–n junction device and its zero-field resistance.
From: Edge mixing dynamics in graphene p–n junctions in the quantum Hall regime
(a) Upper panel: optical picture of the present graphene device. The source and drain electrodes are attached to the graphene. A top-gate electrode is placed on the insulating layer, PMMA (blue part) covering graphene. Lower panel: the optical picture of the graphene device before the metal deposition. (b) Schematic picture of the experimental set-up for the resistance and noise measurement. A resistor of 1 kΩ and a capacitor of 1 μF are inserted in parallel to the graphene device to reduce the impedance. Another resistor of 1 MΩ is placed in series to reduce the external noise. These components are placed in the low-temperature environment at 1.6 K. We measured the voltage noise using a digitizer. (c) Image plot of the two-terminal resistance as a function of Vtg and Vbg at 0 T. The carrier density of the two regions can be controlled almost independently and the device is tuned to either unipolar or bipolar regime. (d) Cross-sections of the image plot of c at Vbg=22, 16, 4 and −5 V.
