Fig. 5: Electronic and Optical SRAM and DRAM architectures.
a Electronic 6T SRAM cell, b optical SRAM cell implementation according to ref. 22, c electronic DRAM cell, d optical DRAM cell with recirculating fiber loops 48, and e pulse trace in write mode operation of optical SRAM cell at 10Gb/s: (top to bottom) (i) inverted access bit (\(\overline {Access}\)), (ii) incoming BitLine (BL) signal, (iii) inverted BitLine \(\overline {(BL)}\), (iv) set and (v) reset signals, respectively produced as the AND product between BL and \(\overline {BL}\)with Access, and finally, (vi) RAM cell memory content
