Fig. 1: The concept of growing in-plane InP sub-micron wire and membrane array on (001) SOI wafers.
From: A monolithic InP/SOI platform for integrated photonics
a, b Schematic of selective lateral hetero-epitaxy of InP sub-micron wires and membranes. c Cross-sectional schematics of each step. (i) Si device layer patterning. (ii) Oxide encapsulation (oxide deposition and opening). (iii) Anisotropic Si wet etching to form Si undercut. (iv) Selective epitaxy of in-plane InP sub-micron wires and membranes. Definition of InP sub-micron wires and membranes dimensions: the width refers to the dimension along lateral epitaxial direction, while the length denotes the orthogonal dimension of the oxide patterns defined by lithography, as indicated in step iv
