Fig. 1: Fabrication flow and high resolution SEM images of nanogap devices.

a Simplified fabrication flow of nanogap electrodes. The fabrication process began by (1) growing 500 nm of thermal oxide on a Si wafer. (2) Then, 200 nm of Au (with a Cr adhesive layer) was deposited and patterned to define the lower electrodes. (3) Next, a SiO₂ layer (~4.5 nm) was deposited using plasma-enhanced ALD at a 200 °C chuck temperature, and an additional α-Si layer (~1.5 nm) was deposited, which together determined the thickness of the spacer layer. The thickness of atomic layer deposition (ALD) SiO₂ and DC sputtered α-Si was verified using ellipsometry (Woollam Variable Angle Spectroscopic Ellipsometer (VASE)), and the thickness of the entire spacer layer was verified using SEM imaging. (4) On top of the spacer layer, an upper Au electrode layer (200 nm) was sputtered and then (5) subsequently patterned using standard lithographic techniques. Finally, (6) the spacer stack layers were etched away through SF6 plasma dry etching, thereby forming an air gap along the edges of the top electrode. b SEM images of the fabricated device, where the overlap area was reduced to suppress parasitic current flow. The device footprint was 0.36 mm², and the overlap area was ~16 μm² (middle). The nanometer-scale dimension of the air gap formed between the upper and lower electrodes was confirmed by high-resolution SEM imaging