Fig. 3: Working principle and architecture of the in-plane domain wall memory.
From: Next-generation ferroelectric domain-wall memories: principle and architecture
a and b Sketches of two-terminal and three-terminal mesa-like cells with bipolar domain information written at voltages higher than Vcb (left panel) and lower than Vcf (middle panel) that were applied to the L and R electrodes, respectively. The right panels show the “off” and “on” current states from the I–V curves assumed in Ohmic conduction at a read voltage applied between L and R when 0 > VR > Vcf for the two-terminal cells and applied between M and R with VR > Vcf for the three-terminal cells, accompanied by erasure/creation of the domain walls indicated by dotted red lines. VLR, for example, denotes the voltage that is applied to L when R is grounded and M is floating. The thick arrows indicate domain orientations, and the thin arrows indicate voltage sweeping directions in the I–V curves. c 1T–1R and cross-bar architectures proposed for the two-terminal and three-terminal memory cells, respectively
