Fig. 1: Brief introduction to 3D microfabrication technology and 3D integration technology.
From: Manufacturing of 3D multifunctional microelectronic devices: challenges and opportunities
a Schematic illustrations of typical 3D cantilever fabrication assisted by etching of the sacrificial layer and SEM images of a 3D MEMS mirror15. a is adapted with permission from ref. 15. (Copyright © 2018 IEEE). b Bottom–up integration process for the fabrication of NW resonator arrays18. b is adapted with permission from ref. 18. (Copyright © 2008 Nature Publishing Group). c, d Schematic illustrations of the fabrication process and SEM images of 3D stacked GAA transistors obtained by selective etching of sacrificial layers19 and alternating etching-passivation steps20. c–d are adapted with permission from refs. 19,20. (Copyright © 2008 & 2014 IEEE). e–g Three types of 3D integration technology and images of some representative examples: e stacked-die with wire bonding and package-on-package stacking22, f memory stacking with TSVs26, g wafer-to-wafer bonding (bumpless)27. e–g are adapted with permission from refs. 22,26,27. (Copyright © 2009 IEEE, 2016 IEEE & 2006 IEEE.)
