Fig. 3: Electric-Double Layer Transistors. | NPG Asia Materials

Fig. 3: Electric-Double Layer Transistors.

From: On-demand tuning of charge accumulation and carrier mobility in quantum dot solids for electron transport and energy storage devices

Fig. 3

a Schematic of an electric-double-layer transistor (EDLT) of PbS QDs using [EMIM][TFSI] ionic liquid as the electrolyte gate to probe the intrinsic carrier transport across different types of assemblies. b Comparison of the linearly plotted ID-VREF transfer characteristics of the ionic-gated FETs with PbS QDs assembled by different methods, showing a gradual increase in the electron conductivity with the enhancement of the QD assembly order. c Logarithmic plot of the transfer characteristics to emphasize the current modulation ratios. Different from the observations of the solid-gate FETs, the EDLT with the dip-coated assembly demonstrates a substantial electron enhancement. d Comparison of gate-voltage-dependent electron densities accumulated by EDL gating of QD assemblies prepared by three different methods. The carrier density value was deduced from the gate displacement current measurement. e Carrier-density-dependent electron mobility of the three EDLTs. While the EDLT with the liquid/air interfacial assembly demonstrates the highest electron mobility, the transistor with the dip-coated QD assembly affords the highest maximum accumulated carrier density.

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