Fig. 2: Fabrication steps and electrical measurements of proposed Te-nanonet transistor. | NPG Asia Materials

Fig. 2: Fabrication steps and electrical measurements of proposed Te-nanonet transistor.

From: Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

Fig. 2

a, b Sequential fabrication process of the Te-nanonet-based transistor in schematic and real-image layouts, respectively. c Transfer curve (ID–VG) of a single Te-nanonet-based transistor at VD = − 10 V. d Output curve (ID–VD) of the same device at different gate voltages ranging from 10 V to −50 V with a step of −10 V.

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