Fig. 1

Structure and enhancement characteristics of the device. a Schematic top and cross-sectional views of the device. The front and back (buried) oxides, and the SOI are 20-nm, 390-nm, and 18-nm thick, respectively. The Si channel width W in the T-branch region is about 30 nm. The length of the emitter and collector gates are about 60 nm and the spacing between the two gates L, which is an important parameter in the present study, is about 90 nm. b Scanning electron microscope image of a sample device with the same structure^26,27 as those measured here (before the upper-gate formation). Note that the Si channel and the gates are covered by oxide, and thus their actual widths are narrower than the appearance in the image. c Energy diagram of the device. E_F and E_C are the Fermi energy and the conduction band edge, respectively. Open blue dots represent holes. d Electron flow at small |V_E| (left) and large |V_E| (right). The arrows indicate the direction of the electron flow. e R_I ( = |I_C/I_E|) as a function of the collector gate voltage V_CG measured at 8 K. Inset shows the log-scale plot of the R_I. f R_I as a function of V_CG for the emitter-gate voltage V_EG = – 1.8 V using the temperature T as a parameter