Fig. 1
From: Enabling thin-film transistor technologies and the device metrics that matter
Thin-film transistor architecture and the important device metrics. a Generic schematic of a staggered bottom-gate TFT. b Conceptual transfer curve (solid line) and characteristic spread (shaded region) attributed to threshold voltage fluctuations for a large set of TFTs. c Conceptual illustration of the transfer curve shift due to continuous bias application. d Approximate plot of the circuit yield as a function of the number of concatenated unipolar NOT gates using σVT as the only variable parameter. The plot shows that the less VT fluctuates (i.e. σVT becomes smaller), the larger the number of logic gates/TFTs that can be integrated onto the same circuit
