Fig. 2
From: All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration
Surface plasma-oxidized WSe2 TFT and electrical characterization. a Device schematic showing a four-layer WSe2 and 2.2 nm WO3 on SiO2/p + Si layer with gate length (Lg) = 1.80 µm and width (W) = 2.05 µm. b Transmission electron microscopy image of the device contact region, after post-contact plasma oxidation, revealing the presence of WO3 underneath the metal contacts. c Id–Vg plots for four-layer thick device with and without WO3. d Id–Vd characteristics after plasma oxidation for different gate voltages. e Effective Schottky barrier height extraction from low-temperature transfer characteristics and Arrhenius plot. At flat band condition, the curve deviates from linearity and the corresponding activation energy becomes the Schottky barrier. f Benchmark plot showing the performance of plasma-oxidized p-FET versus other reported data. Ion is determined at Vd = −0.5 V
