Fig. 4 | Nature Communications

Fig. 4

From: All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration

Fig. 4

1T1R configuration and characterization. a 3D schematic view of 1T1R structure with flaked WSe2 transistor and printed WSe2 ReRAM and the corresponding circuit representation. The photo image of 3× WSe2 ReRAMs printed using low-temperature aerosol jet printing method, which is linked up to the fabricated WSe2 TFT on a single chip is also shown. b I–V switching plot for 1T1R configuration, where the switching current is limited by the transistor drive current

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