Fig. 6: Electrical properties of parallel wires.
From: Templated dewetting of single-crystal sub-millimeter-long nanowires and on-chip silicon circuits
a Scheme of the field effect transistor (FET) wires device (doping about 3\(\times\)10\({}^{18}\) cm\({}^{-3}\), n-type). b SEM images of the electric contacts (left part, source, gate and drain, respectively S, D, and G) and a detail of the S contact (right). The gold contact (Au) and the SiO\({}_{2}\) partially covering the wires are highlighted. c Electrical transport characteristics of 15 parallel wires (S-D current versus S-D voltage curves recorded at different G voltage. Inset: S-D current versus G voltage recorded at source-drain voltage \({V}_{{\rm{SD}}}\) = 2 V for 15 parallel wires.
