Fig. 1: Structure schematic and basic electrical properties of InSe FET. | Nature Communications

Fig. 1: Structure schematic and basic electrical properties of InSe FET.

From: Oxidation-boosted charge trapping in ultra-sensitive van der Waals materials for artificial synaptic features

Fig. 1

a Schematic diagram of the InSe FET exposed to ambient conditions, in the presence of several gas molecules (such as H2O or O2). The Si substrate serves as the gate electrode and the covered In film acts as the surface dopant. b AFM image and the corresponding height profile of the InSe channel. The inset shows the typical OM image of the InSe FET, where the length and width of the InSe channel are 13 and 31 μm, respectively. c, d Transfer characteristics and the gate leakage curves at drain voltage Vds = 0.1 V for the 15 representative InSe FETs under the vacuum and ambient conditions, respectively. Note that the arrows mark the directions of the gate voltage sweep and ΔVth means the threshold voltage shift. e Histogram of the threshold voltage shift for InSe V- and A-FETs and the Gaussian fit (solid lines) based on the statistical database.

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