Fig. 4: Wafer-scale uniformity and the CMOS inverter integration with n-channel IGZO TFTs.
From: High-performance p-channel transistors with transparent Zn doped-CuI
a Photograph of CuI:Zn5mol% TFT array on a 4-inch Si/SiO2 (100 nm) wafer substrate (dot line means measurement area). b, c Statistical results of μsat and Ion/Ioff obtained from 96 TFTs across the array. d–f Voltage transfer, gain, current characteristics, and noise margin (NM) extraction of the complementary inverter based on n-type IGZO/SiO2 and p-type CuI:Zn/SiO2 TFTs.
