Fig. 4: CuInSe₂-CQD-based inverter realized using complimentary p- and n-channel FETs.

a Processing steps used to fabricate a complementary metal-oxide-semiconductor (CMOS) inverter based on p- and n-channel CuInSe₂ CQD FETs (PFET and NFET, respectively). After cleaning a p⁺⁺ Si substrate (gate electrode), we deposited a 70-nm layer of Al₂O₃ by ALD to serve as a gate dielectric. Gold and then indium source and drain electrodes were deposited via thermal evaporation to define the PFET and NFET, respectively. The PFET and NFET channel widths are 3 and 1 mm, respectively. The channel lengths are the same (100 µm) for both FETs. The CuInSe₂ CQD layer was deposited onto the substrate with the prepatterned electrodes via sequential spin-coating and ligand exchange using NH₄I/methanol followed by washing with methanol. The device was then annealed at 180 °C to allow for indium diffusion into the CQD layer within the NFET channel. Finally, the device was encapsulated in a thin layer of Al₂O₃ by ALD. b The schematic depiction of the fabricated CQD CMOS inverter (not to scale). CQDs form a continuous film on top of a substrate with prepatterned PFET and NFET electrodes and connecting metal circuits that define the device function. The red and green areas show the region of the CQD film that act as, respectively, p- and n-type channels. c The voltage-transfer characteristic (VTC) of this device for V_DD = 5 V (solid red line). The dotted black line corresponds to V_out = V_in. The dashed blue line is the first derivative of the VTC. Inset is a top-view photograph of the substrate with three inverters (scale bar is 5 mm). Source data are provided as a Source Data file.