Fig. 2: Electric transport properties of vdW FeFETs.
From: Van der Waals engineering of ferroelectric heterostructures for long-retention memory
a Schematics of the measurement setup used to characterize the internal 2D FET. b Internal-gate Ids−Vint characteristics of 2D FET at various gate voltage ranges measured with Vds = 0.5 V and top gate floating. The device has a three-layer MoS2 channel and an 87-nm-thick CIPS layer. c Internal-gate SS−Ids characteristics (left) and top-gate SS−Ids characteristics (right) for the forward and reverse sweep. d Schematics of the measurement setup used to characterize the vdW FeFET. e Top-gate Ids−Vtg characteristics of the vdW FeFET at various gate voltage ranges measured with Vds = 0.5 V and internal gate floating. f The Ids−Vds curves for the forward and reverse Vtg step direction with the internal gate floating.
