Fig. 9: Acceleration of multibit vector-matrix multiplication.
From: Self-rectifying resistive memory in passive crossbar arrays
a Configuration of a mapped weight matrix w (M × N) and multibit vector x (here, 3-bit). Elements x[i] are time-multiplexed, so that the multiplication delay is proportional to the bit-width of elements x[i]. b Timing diagrams of the signals to calculate w[:,i]·x for a given i with multibit elements including x[0] (=b101), x[1] (=b010), and x[29] (=b111). The resulting currents in the three time divisions (j[00], j[01], and j[02]) are first quantized by the SAs and subsequently multiplied by 1, 21, and 22, respectively, and summed in the processing elements (PEs).
