Fig. 1: 2T–1C unit cell and circuits fabricated on a wafer-scale MoS2 film. | Nature Communications

Fig. 1: 2T–1C unit cell and circuits fabricated on a wafer-scale MoS2 film.

From: An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations

Fig. 1

a Wafer-scale MoS2 continuous films are batch-synthesized by a CVD method. b Raman spectra from different positions on the MoS2 film. c Transfer characteristics for 24 MoS2 transistors spread on a 2 in. wafer. d Microscope image of the fabricated 2T–1C cell. Scale bar: 100 μm. e Circuit schematic of a 2T–1C cell containing storage and calculation modules. f 3D schematic illustration of a 2T–1C unit cell, including two MoS2 FETs and one capacitor. g Circuit diagram of the proposed 2T–1C cell array. h A typical diagram of a matrix convolution operation.

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