Fig. 2: Characterization of the 1T–1C storage module. | Nature Communications

Fig. 2: Characterization of the 1T–1C storage module.

From: An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations

Fig. 2

a Schematic diagram of the electrical circuit used to measure the 1T–1C storage module (shadow area). The equivalent circuit in the dashed box equals an external oscilloscope connected to the capacitor. b Input voltage waveform (Vw, Vre) and readout current (IQ) vs. measurement time. c IQ spikes at Vre = 3 V while Vw−write ranges from 2.4 to 3 V in 0.1 V steps. d Calculated retained charge (Qread) in the capacitor as a function of Vw−write (compared with Vw−read = 2.0 V when IQ = 0 A).

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