Fig. 3: Characterization of the 2T–1C unit cell. | Nature Communications

Fig. 3: Characterization of the 2T–1C unit cell.

From: An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations

Fig. 3

a Schematic diagram of the circuit used to gather measurements from a 2T–1C unit cell. b A complete storage and calculation operation for a 2T–1C unit. The input voltage (Vw, Vre, Vx) and drain current (Id) are shown vs. measurement time for a 10 s cycle. The magnified inset shows details of the refresh operation. c The output characteristics for T2 with Vg ranging from 2.4 to 3 V in 0.1 V increments. d Drain current Id in T2 with Vx ranging from 0.05 to 0.35 V, where Vw = 2.4 V. The bars in the right panel indicate the variation of Id for each curve after T1 is turned off. e Transfer characteristics of T2 with Vx ranging from 0.05 to 0.35 V in 0.05 V increments. f Drain current Id in T2 with Vw ranging from 2.4 to 3 V, where Vx = 0.1 V.

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