Fig. 4: Demonstration of multiply accumulate operation using two 2T–1C cells. | Nature Communications

Fig. 4: Demonstration of multiply accumulate operation using two 2T–1C cells.

From: An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations

Fig. 4

a Schematic showing two identical 2T-1C cells. The sources of the two cells are connected to sum the drain current. b Top graph: a test multi-step voltage waveform applied to Vx, ranging from 0.005 to 0.35 V with 0.05 V increments. The pulse width is 0.1 s. Bottom graph: The corresponding Id waveform, while Vw is fixed at a series of values. Both Vx and Vw exhibit eight distinguishable voltage levels (3 bits). c The output current Id as a function of Wc, and the fixed input Vx ranges from 0 to 0.35 V with 0.05 V increments. d The output current Id is plotted as a function of Vx under different Wc values. e The measured Id values as a function of their calculated Y(Wc × Vx) for two different 2T–1C cells on one MoS2 wafer. f The total output current Isum as a function of Ysum from the two different 2T–1C cells.

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