Fig. 2: Design of a vertical field-effect transistor (VFET) with nanomesh scaffold.

a Fabrication process flow for the hexagonal hole array nanomesh scaffold through nanosphere lithography, O₂ plasma etching and transfer process. Nanosphere was transferred onto an Al-deposited SiO₂/Si wafer. The geometrical parameters of the resulting nanostructure could be tuned by the diameter of the polystyrene nanospheres and the etching dose of the oxygen plasma. The aluminum layer was removed by solution etching, and the nanomesh scaffold was then transferred onto the targeted substrate. b Graphene/nanowires network fabrication procedure. The transferred monolayer graphene was patterned by photolithography and O₂ plasma to form the bottom source electrode. PTCDI-C8 nanowires network was transferred on the graphene layer through a vacuum-assisted stamp method. The floating nanomesh scaffold was then transferred directly onto the PTCDI-C8 network as the top drain electrode. c Photograph of a large-area nanomesh scaffold on Al-deposited silicon wafers. d The resulting PTCDI-C8 nanowires VFETs with nanomesh scaffold. e AFM image (topography) of the transferred PTCDI-C8 nanowires network. f AFM image of the final vertical-channel PTCDI-C8 device bearing the nanomesh scaffold. g SEM image of nanomesh electrodes covering PTCDI-C8 nanowires network, scale bar: 5 μm. h Cross-sectional SEM image of a PTCDI-C8 nanowires based vertical device, scale bar: 2 μm. i Zoom-in SEM image of the same sample in h, the thickness of the PTCDI-C8 nanowires network is around 2 μm, scale bar: 2 μm.