Fig. 1: Image processing array with switchable functions. | Nature Communications

Fig. 1: Image processing array with switchable functions.

From: An application-specific image processing array based on WSe2 transistors with electrically switchable logic functions

Fig. 1

a Macroscopic image of the bonded device on the carrier, which consists of 3 × 3 pixels, scale bar: 2 mm. b The optical image of the TSC image processing pixel array, scale bar: 50 μm. We use P1-P9 to mark the ports of each pixel unit. The input 1, input 2, output and Op-instruction ports are coloured by purple, green, grey and red respectively. c Schematic circuit diagram of the pixel processing array. With different Op-Instruction inputs, image intersection and comparing functions are implemented. d Top part: The cross-sectional high-resolution TEM image. The scale bar is 5 nm. Bottom part: Schematic diagram of the single-pixel processing unit. The drain and source of the device serve as the OP-Instruction and output ports, the top gate and bottom gate serve as input 1 and input 2. With the Op-instruction signal input, a single transistor can perform switchable logic functions.

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