Fig. 2: Implementation of the eRNR.

a Schematic of an N-neuron eRNR. Given an input u(k), first, an operational amplifier generates another signal source −u(k) or negative input. The switch array S₁ to S_N determines the input weights W_in by selecting a positive or negative source for each multiplexer. The multiplexers m₁ to m_N and m₁’ to m_N’ are involved in the electrical implementation of pre- and post-neuron rotors, respectively. The log₂N-bits counter outputs an address signal to sequentially activate the channels of each multiplexer at switch intervals τ_r. Based on the distinct sequence of neuron connections (in₁ to in_N for the input and out₁ to out_N for the output), the behavior of the multiplexer array is equivalent to that of a rotor cyclically shifting connections between neurons and input/output channels. The sequence for output channels is a mirror version of that of input channels, which complies with the common-directional rotation principle in RNR theory. b General schematic of the dynamic properties required for a neuron in an RNR. When a neuron input \({\gamma({{{{\bf{R}}}}^{{{{\rm{k}}}}-1}})^{{{\rm{T}}}}{{{{\bf{W}}}}_{{{\rm{in}}}}{{{\bf{u(k)}}}}}}\) that has been processed by a pre-neuron rotor and input weights are provided, the neuron performs nonlinear transform f, integration (feedback line), and leakage (decay factor d) operations on the signal. a(k) is the neuron output at the kth step. c A dynamic neuron in the eRNR. C_int and R_int serve as integrators. The rectifying diode D_ReLU provides an activation function similar to a nonlinear ReLU function. Finally, high resistance R_leakage is added to control the current leakage rate, that is, the decay factor d in Eq. (6). d, e The nonlinear properties (d) and dynamic integration (e) of the neuron for R_int = 10 kΩ, C_int = 1 µF, and R_leakage = 100 kΩ. D_ReLU is a germanium diode with a forward voltage of approximately 0.3 V. f Schematic of a complete eRNR system that includes M parallel N-neuron RNRs. The total length of the state matrix is M × N. The voltage signal of each state channel is multiplied by the trained output weights stored in a memristor array to yield the final computing result.