Fig. 2: FeFET-based analog synapse. | Nature Communications

Fig. 2: FeFET-based analog synapse.

From: Neural sampling machine with stochastic synapse allows brain-like learning and inference

Fig. 2

a Schematic of a stand-alone FeFET-based analog synapse. The channel conductance can be modulated by applying write pulses ±Vwrite to the gate of the FeFET while reading out the conductance state is achieved by applying a small read voltage Vread to the gate terminal. b Experimentally measured conductance modulation in a 500 nm × 500 nm high-K metal gate FeFET fabricated at 28 nm technology node. An amplitude modulation scheme is used where positive and negative write voltage pulses Vwrite of increasing amplitude from 2.8 V to 4 V and pulse widths of 1 μs are applied to modulate the conductance of the FeFET. c Measured continuous change in the conductance state of the FeFET upon applying multiple potentiation and depression pulses of varying amplitude. d The FeFET-based analog weight cell is modeled in the NSM by fitting the conductance update scheme for both potentiation and depression with the closed-form expression as shown in the figure. WL word line, BL bit line, SL source line, Vin input voltage, Iout output current, Vwrite write voltage, G conductance, LRS low resistance state, HRS high resistance state.

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