Fig. 1: Fabrication of topology-optimized silicon dielectric bowtie cavity (DBC).

a Rendering of the DBC design generated by tolerance-constrained topology optimization. The normalized ∣E∣-field is projected on the faces defining the three symmetry planes of the design. b Zoom-in of the solid silicon bowtie exhibiting a strong field confinement due to the bowtie bridge dimension of 8 nm. c 40° tilted scanning electron microscopy (SEM) image of a fabricated cavity. d Global geometry-tuning, δ. Each air (black) pixel (1 nm²) inside a δ-outline is exposed uniformly with electron-beam lithography; hence, air features defining the device are uniformly tuned. e–g 40° tilted SEM images of bowtie region for δ = { − 2, − 4, − 6} nm. We measure the mean width of the fabricated bowties to be (8 ± 5) nm, (10 ± 5) nm, and (16 ± 5) nm for figures e, f, and g, respectively, noting the variation in width along the z-direction caused by the scallops and ~1° negative sidewall angle represented by the uncertainty as discussed in the main text.