Fig. 1: Back-bias reconfigurable field effect transistor (BB-RFET) integrated on 300 mm wafers using 22 nm FDSOI technology.
From: Three-to-one analog signal modulation with a single back-bias-controlled reconfigurable transistor
a Schematic image of a single device with materials and contacts, comprising source (S), drain (D), front-gate (FG), and a back-bias (BB) contact. b Three distinct operation modes accessible by changing the applied back-bias (VBB). c Distribution of minimal subthreshold swing SS in ambipolar mode for VDS = 0.1 V measured at devices with varying width as compared to Fig. 1b. Boxplot shows median with 25% and 75% quartile. Outliers are indicated. d Full families of transfer characteristics for n-type (blue) and p-type (red). VDS is varied from 0.1 to 1.5 V in steps of 0.1 V. e Family of output characteristics in n-type operation. f Family of output characteristics in p-type operation. w is the channel width in all plots.
