Fig. 2: Fabrication process of a patterned few layer graphene (FLG) gate electrode.
From: Engineering high quality graphene superlattices via ion milled ultra-thin etching masks
a Transmission electron microscope (TEM) image of a thin suspended silicon membrane which has previously been milled with a He focused-ion beam (FIB). b The membrane is transferred with a polypropylene carbonate (PPC) coated polydimethylsiloxane (PDMS) stamp onto a FLG flake coated with a thin layer of poly(methyl methacrylate) (PMMA). c The sample is etched following a standard O2/Ar reactive ion-etching (RIE) process, followed by a lift-off process to remove the membrane and clean the PMMA layer underneath (d). e Atomic force microscopy (AFM) topography image of a 16 nm period triangular lattice on a FLG flake. The scale bar is 50 nm. f Fast Fourier transform (FFT) of a larger region of the same AFM image in panel e, including 2555 lattice sites.
