Fig. 2: Chip fabrication and characterization.
From: High-order tensor flow processing using integrated photonic circuits
a Photograph of the packaged PTFP chip. Optical signals enter and leave the chip via an edge-coupled fiber array. b Layout of the PTFP chip. Four wavelengths are combined in the WDM. Two optical delay lines (ODLs) are deployed to provide three delay steps. Before and after each ODL, weighting banks with four MRRs in each are implemented. c Photograph of the WDM. d Transmission spectra of the WDM. e Regional photograph of the MRR array. f Transmission spectrum of the MRR array. Different voltages (0–1400 mV with 200 mV/step) are applied on the second MRR. A similar result can be obtained when voltage is applied to other MRRs. g Transmission rate of all 12 MRRs on the chip under voltage tuning. These curves represent weight–voltage mappings after normalization. The original resonance points of MRRs are different because of fabrication deviation.
