Fig. 5: CMOS-like inverter based on gate tunable correlated insulator.
From: Unconventional correlated insulator in CrOCl-interfaced Bernal bilayer graphene
a, b PMOS- and NMOS-like field effect curves in the same gate range, swept along dash lines in Supplementary Fig. 12a, b. Inset of each shows the log scale of the same data. c Schematic picture of the BLG/CrOCl CMOS logic inverter. Here, \({V}_{{{{{{{{\rm{set}}}}}}}}}^{{{{{{{{\rm{P}}}}}}}}}\) and \({V}_{{{{{{{{\rm{set}}}}}}}}}^{{{{{{{{\rm{N}}}}}}}}}\) denote the setting voltages to maintain the shape of the desired P- or N-type field-effect curves. d The performance of a typical graphene inverter. e Source-drain current Idd flowing in the graphene inverter in d as a function of input voltage during working. f Output voltage Vout as a function of input voltage Vin at different temperatures, with the supply voltage Vdd fixed at 200 meV. Inset shows the gain for each curves in f.
