Fig. 5: Hysteresis-free MoS2 FETs and low-power NMOS inverters using Bi2SiO5 as high-κ top-gate dielectrics.
From: Vertically grown ultrathin Bi2SiO5 as high-κ single-crystalline gate dielectric
a Schematic illustration of the top-gated MoS2 FETs on SiO2/Si substrate with Bi2SiO5 as the top-gate dielectric. b Typical dual-sweep transfer curves of the MoS2/Bi2SiO5 FET measured under different Vds from 0.05 to 1 V, showing an ideal SS value of ~62 mV/decade and ignorable gate hysteresis. The Insert is the OM image of a fabricated MoS2 FET with Bi2SiO5 as the gate dielectric. c Corresponding output characteristics (Ids–Vds curves) of the device measured by varying the Vg from 0.5 to −0.6 V with a 0.1 V step. d Extracted SS value versus Ids characteristics of the device in b, showing a low SS value (<70 mV/decade) for a wide Ids range. e Dual gated transfer curves of the MoS2/ Bi2SiO5 FET under different back-gate voltages (VBG) from 5 to 0 V. f The extracted threshold voltage Vth from e as a function of VBG. The linear fitting yields a slope of −0.0097 and a high dielectric constant of ~32.3. g The thickness-dependent dielectric constant of Bi2SiO5 extracted by dual-gate measurement on Bi2SiO5/MoS2/SiO2/Si FET. The dotted curve is a visual guide. h Transfer curves of the MoS2 FETs with different thickness Bi2SiO5 as the top-gate dielectrics, showing a trend of smaller Vth for thinner Bi2SiO5 thickness. The Vds is 0.5 V, and no VBG is applied. i Measured output voltage (Vout) and gain as a function of input voltage (Vin) of an NMOS inverter based on two MoS2/ Bi2SiO5 FETs under different supply voltage (Vdd) from 2 V to 0.5 V.
