Fig. 2: Comparison of the program/erase (P/E) performance of memory cells with 1 T edge or Cr top contacts.

a, b Schematic illustration (a) and false color scanning electron microscopy (SEM) image (b) of the paired memory cells on the same vdW heterostructure. The float gate (FG) is made by etching an exfoliated few-layer graphene. Thus, the paired memory cells exhibit identical thickness combination for each layer and differ only in contact configuration using 1 T edge (EC) or Cr top contact (TC). c, d Map of the attained ON/OFF ratio of memory under different voltage pulse conditions when changing both the amplitude and pulse width: 1 T edge contact (c) and Cr top contact (d). The P/E condition that guarrantees a high ON/OFF ratio = 104 in top contacted memory cell is marked in both figures for a guidline (dash line) when comparing their operation speed. e, f P/E behavior (e, f) of >20 memory cells under ultrafast electric pulse (10 ns for program, 100 ns for erase) and varying operation voltage. The operation voltage was normalized according to the thickness of tunneling hBN to reflect the electric field strength at the tunneling layer. On the right panel of e, f, the cumulative probability is counted if an ON/OFF ratio ≥102 is attained by the applied ultrafast P/E pulses.