Fig. 3: Mixed-signal neuromorphic hardware system based on PBFCL₁₀ neuromorphic matrix and digital circuit components.

a Photograph of the hardware system, composed of a PC-based user interface, an FPGA controller, and a PCB operator loaded with a DAC, an ADC, a MUX, TIAs, a power voltage source, an I/O header and a 32 × 32 PBFCL₁₀ neuromatrix chip. b PC-based user interface for synapse hardware operation. The left panel shows the devices selected for operation and their conductance states in different colors. Upon inputting the column and row numbers of the selected organic neuromorphic devices, program voltages, compliance currents, and numbers of voltage pulses through the user interface, the evolution of the device resistance can be directly modulated by the FPGA-PCB based system and shown in the bottom right panel of the user interface. The blue rectangle in the upper right panel is the start button to execute the set and reset tasks, respectively, while the orange rectangle is the stop button to arbitrarily end the current task. c QC evolution of 100 devices randomly selected in the 32 × 32 neuromorphic matrix chip. In-operando updated conductance matrices, theoretical conductance matrices predicted by the synaptic weight updating scheme of BHNN as well as the conductance deviation matrices of the 1024 PBFCL₁₀ devices in the 32×32 crossbar array during d initialization and after e 200 and f 420 iterations, respectively.