Fig. 3: Experimental demonstration of the steep-slope TS-VTFETs.
From: Steep-slope vertical-transport transistors built from sub-5 nm Thin van der Waals heterostructures
a Schematic of the MoS2/MoTe2 TS-VTFET, where the source contact is connected to the MoS2 layer. b Typical threshold resistive switching of the TaOx/TaOy/TaOx TS cell with ultra-low leakage current and very steep current switching slope. Vhold, Icc, and Vth: metal filament holding voltage, compliance current, and threshold voltage triggering the filament formation, respectively. The arrows indicate the current sweeping directions. c Schematic drawing of the Ag filament formation and rupture process in the TS cell. d Output curves of the VTFET and the TS-VTFET at Vg = 1 V. e Transfer characteristics of the VTFET and the TS-VTFET during the forward sweeping process at room temperature. The dashed black line indicates the “cross points” below which the instrument limit induced noisy current contaminates the measured Id. In our case, the instrument limit current cross points occur at or below 30 fA for all the transfer curves measured. f Point SS calculation for both VTFET and TS-VTFET as a function of the Id during forward gate voltage sweeping. The dashed black line indicates the SS = 60 mV/dec limit.
